Many techniques have been developed for repairing defective rows or columns in memory devices by using redundant rows or columns to replace faulty bit cells or lines. Using redundancy to improve semiconductor yields is well known in the art. The address(es) of the defective elements are stored in a non-volatile way, generally by way of fuses. When such an address is fed into the chip, it selects a redundant element and the original defective element is ignored or explicitly disabled. The location of the spare element is governed solely by layout convenience.
Prior art proposals for applying row redundancy for memories include disabling a defective row and replacing it with a spare row located at the outer boundaries of the memory array. Other redundancy schemes, as described in U.S. Pat. No. 6,249,467 teach replacement of a defective row with a spare row that can be in the same memory block or in a different block. This redundancy scheme poses a problem for the normal operation of Content Addressable Memory (CAM) cell arrays.
A CAM is distinguished from other memory devices in that the memory cells are connected to match lines. Rows of Match lines are fed into a priority encoder which provides either one or a plurality of addresses sorted by a priority. Priority is normally given to the row with the lowest physical addresses. Thus, the relative location of rows of memory cells and their associated match lines is important. Accordingly, a remapped row of cells requires a corresponding remap of the priority encoder. The complexity of the logic to implement such a mapping will be evident to those skilled in the art.